On 07/13/2016 01:40 PM, smf wrote: > On 12/07/2016 17:59, Jim Brain wrote: >> >> I think I tied OE to the 2364 select line, so if your use case uses >> CE, you'll have to cut a trace, and if it uses both, then you're into >> an OR gate, which my design does not support. >> > > I'd have thought 2364 pin 20 (_CE) would make more sense to be connected > to 2764 pin 20 (_CE). This would cover the case for _OE being grounded > as well as when _CE & _OE are tied together. In man circuits they control the EPROM through _OE and tie _CE to GND since that allows you to get away with slower EPROMs. This way the EPROM is always aktive and decoding addresses, just the output buffers are disabled. So you can hide quite a bit of the access time inside the delay for the decoder that selects the EPROM. Downside: higher power consumption with the old NMOS types. Doesn't really matter with CMOS. If _CE & _OE are > independently controlled then you probably ought to add a hex buffer > with _OE1 and _OE2 and feed _CE and _OE to it. A simple OR gate (74LS32 for example) will tie _OE and _CE together and produce the correct signal for a 2364. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2016-07-13 13:00:10
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