> On 2016-04-23, at 07:44, didier derny <didier@aida.org> wrote: > >>> for the GAL I use ISPLever from lattice Do you write the HDL code yourself there or do you use the schematics editor and let the tool generate VHDL/Verilog/Abel/... ? >> Are GALs still a viable option for a PLD today? > I still find them without any problem for prototype > but I'm not planning any production If there is a GAL (16V8 for example) which has eight inputs and eight Output Logic MacroCells, can some of those OLMCs be configured and used as inputs too? -- SD! Message was sent through the cbm-hackers mailing listReceived on 2016-05-25 20:00:02
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