1565 control chip replacement in CPLD

From: Michał Pleban <lists_at_michau.name>
Date: Fri, 13 May 2016 22:19:23 +0200
Message-ID: <573636CB.6070102@michau.name>
Hello!

I have finished today the replacement control chip for the 1565 drive.
It turned out that I do not need the "disk inserted" signal, because if
I just fool the computer into thinking that a disk is always inserted,
everything works (some other signals need to be faked too, notably the
"disk index" signal must be set to 0, otherwise the computer will hang
on disk access if no disk is present).

The design is pasted below in case anyone is interested in CPLD design :-)

Regards,
Michau.

-----------------------------------------------------


Name     drive1565;
PartNo   ;
Date     2016.05.13;
Revision ;
Designer Michau;
Company  ;
Assembly ;
Location ;
Device f1502ispplcc44;

/*
 * C65 serial interface.
 */

pin 11 = SERIO;
pin 12 = LD;
pin 9 = CLK;
pin 8 = RES;

/*
 * Disk drive control signals.
 */

pin 19 = LED;
pin 29 = MOT;
pin 25 = STP;
pin 24 = DIR;
pin 21 = SID;
pin 26 = DS;

/*
 * Disk drive status signals.
 */

pin 31 = DKC; // Unused
pin 17 = RDY; // Unused
pin 28 = IND; // Unused
pin 18 = PRT;
pin 20 = TK0;

/*
 * Input shift register, shifts in the incoming bits
 *  on falling edge of CLK.
 */

pinnode = [IN0..7];

IN0.D = SERIO.IO;
[IN1..7].D = [IN0..6];
[IN0..7].CK = !CLK;

/*
 * Drive selection signal. Hardcoded drive #1.
 */

pinnode = SEL;

SEL = IN2 & IN1 & !IN0;

/*
 * Latch disk control signals from the incoming shift register
 *  on rising edge of LD.
 */

[LED,MOT,STP,DIR,SID,DS].CK = !LD;

LED.D = IN7 # !SEL;
MOT.D = IN6 # !SEL;
STP.D = IN5 # !SEL;
DIR.D = IN4;
SID.D = IN3;
DS.D = !SEL;

/*
 * Reset logic - automatic reset on power up.
 */

pinnode = [RESET1..2];

[RESET1,RESET2].D = 'B'1;
[RESET1,RESET2].CK = 'B'1;
RESET1.AP = RESET2;
RESET2.AP = !RESET1;

[LED,MOT,STP,DIR,SID,DS].AP = !RES # !RESET1;

/*
 * Output enable - if disk selected and high phase of LD.
 */

pinnode = OUTPUT;

OUTPUT = DS # LD;

/*
 * Output shift register - captures signals from disk if LD is high,
 *  then shifts them out on rising edge of CLK if LD is low.
 */

pinnode = [OUT0..5];

// Fake signals to compensate for lack of DKI signal from the drive:
//  DKI (disk inserted) - always 0
//  DKC (disk changed) - always 1
//  IND (index) - always 0

[OUT0..4].D = (LD & [SERIO.IO, 'B'0, 'B'1, 'B'0, PRT])
# (!LD & [OUT1..5]);
OUT5.D = TK0;
[OUT0..5].CK = CLK;

SERIO = OUT0;
SERIO.OE = !OUTPUT;



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Received on 2016-05-13 21:00:02

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