> On 2016-01-22, at 16:09, Gerrit Heitsch <email@example.com> wrote: > > On 01/22/2016 03:46 PM, firstname.lastname@example.org wrote: >> >>> On 2016-01-22, at 15:38, Gerrit Heitsch <email@example.com> wrote: >>>>> >>>>> Remember that VIC will still use the bus though, only the CPU is taken offline with the DMA line! So you have only about 500ns time before you need to free the bus again. >>>> >>>> Sure. You'd need to act the way CPU does - use "half-cycles". >>> >>> There is another problem with the DMA line. It affects AEC and RDY. But the 6510 cannot be stopped in a write cycle. That's why the VIC sets RDY 3 cycles earlier than it needs the bus (3 write cycles in a row is the max that can happen). >>> >>> That means you cannot use the DMA signal for accessing Memory while the 6510 is doing something useful. Sooner or later you will assert it while the CPU is in a write cycle and cause data corruption. >> >> Can't you HLT it first? > > Yes, that would be BA on the Expansionport. But that 3 write cycle rule needs to be taken into account. Right. You can't just assert it at will. >> In any case - as written already - if only PEEKing the locations is needed, then this isn't even needed at all. > > Hm? If you want to grab a Byte from the C64 memory, then you still need to take over the bus Not at all. If I want to write there - that's a different story. But if it's only the CPU, which does the writes, I don't need to take over the bus, I only sip data-bus bits off when CPU does its job. I wrote - I did it before. -- SD! Message was sent through the cbm-hackers mailing listReceived on 2016-01-22 16:02:50
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