On 01/21/2016 09:51 PM, silverdr@wfmh.org.pl wrote: > >> On 2016-01-21, at 21:41, Gerrit Heitsch <gerrit@laosinh.s.bawue.de> wrote: >> >>>>>>> If what you need is mirroring of a portion of C64 ram I have a FIFO >>>>>>> based bus snooping design that could work, but I haven't had a chance to >>>>>>> verify it. >>>>>> >>>>>> I'd also be interested in a design, as I have a few ideas that need such >>>>>> an integration. I had been planning to implement 8 registers in a CPLD >>>>>> with dual port access, but maybe there are better ways to do this... >>>>> How do CPU carts access the RAM? I mean how the external CPUs do it from the >>>>> EXPANSION port. >>>> >>>> using the DMA line (which halts the internal CPU and removes it from the bus) >>> >>> Well, that's what I mean - if all what's needed is to peek a few bytes off some location from time to time? Or is it supposed to be completely invisible to the system? >> >> Remember that VIC will still use the bus though, only the CPU is taken offline with the DMA line! So you have only about 500ns time before you need to free the bus again. > > Sure. You'd need to act the way CPU does - use "half-cycles". There is another problem with the DMA line. It affects AEC and RDY. But the 6510 cannot be stopped in a write cycle. That's why the VIC sets RDY 3 cycles earlier than it needs the bus (3 write cycles in a row is the max that can happen). That means you cannot use the DMA signal for accessing Memory while the 6510 is doing something useful. Sooner or later you will assert it while the CPU is in a write cycle and cause data corruption. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2016-01-22 15:00:10
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