Re: final cartridge for vic 20

From: Nate Lawson <>
Date: Sun, 13 Sep 2015 23:06:29 -0700
Message-Id: <>
Jim sent me the following privately, forwarding to the list


On 9/13/2015 2:43 AM, Nate Lawson wrote:
> Is it possibly a problem that you used the same names here?
To be sure, I changed the names, to no affect.

However. I did achieve success (a night's sleep can do wonders). Here is the code that finally worked:

module test(reset, clock, r_w, data, io2, uart_ce);
inout reset;
input clock;
input r_w;
inout [7:0]data;
input io2;
output uart_ce;  // ignore.  It's just here because my test board has a UART on it, and the uart has an active high CE.

wire [3:0] cart_config1;
assign uart_ce = 0;
assign reg_write = (!r_w & !io2);
assign data = (r_w & !io2 & clock ? {4'b0,cart_config1} : 8'bz);

reg [1:0]reset_ctr = 2'b0;
always @(negedge clock)
   if(reg_write & data[7])
      reset_ctr <= 1;
   else if (reset_ctr != 0)
      reset_ctr <= reset_ctr + 1;

assign reset    =                (reset_ctr == 2'b10 ? 0 : 1'bz);
assign reg_reset =               (reset_ctr != 0 ? 0 : !reset);

register #(.WIDTH(4))    cart_config1_reg(clock, reg_reset, reg_write, {data[3:0]}, cart_config1);


As Greg questioned, it appears to be a race condition.  The 2 bit counter seems to have fixed the problem.  In case folks don't see it:  the counter starts when bit 7 is written and then cycles to 2 and 3 and then 0on succeeding clock cycles.  if the counter is not 0, I protect the reg_reset signal, which means it is inactive for 3 cycles (cycles 1,2,3), and on cycle 2, I reset the machine.  In this way, the protection happens a full cycle before I reset and continues for 1 cycle after I release reset.

I first tried this:

reg flop1 = 0
always @(negedge clock) flop1 <= reg_write & data[7];

reg flop2 = 0
always @(negedge clock) flop2 <= flop1;

assign reset = (flop1 & flop2 ? 0 : 1'bz);
assign reg_reset = (flop1 | flop2 ? 0, !reset);

which, as some will note, won't work in practice because the 6502 must see a reset signal for at least 1 clock cycle, and flop1 & flop2 is only high for 1/2 a clock cycle.

So, my apologies for the semi-useless Verilog list emails. Obviously, always interested in an easier way to do this, but this looks to work.


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Received on 2015-09-14 07:00:07

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