Re: final cartridge for vic 20

From: Jim Brain <>
Date: Thu, 10 Sep 2015 00:24:23 -0500
Message-ID: <>
On 9/10/2015 12:11 AM, Nate Lawson wrote:
> I think the problem is here:
> ###
> assign reset_in =                (reset_en ? 0 : !reset); //if soft reset, 0, otherwise !reset
> register #(.WIDTH(6))                cart_config1_reg(clock, reset_in, cart_config1_reg_ce, data[5:0], cart_config1);  // active high reset.
> ###
> If the external reset line goes low (which it does when you set reset_en to do a soft reset), reset_in goes high and the config register is reset. Just stop passing reset_in to the config register and get it from a different source.
If external reset lines goes low, but I did so with the soft reset 
functionality, then reset_in will be 0, according to the above.  It will 
be that way until the next falling clock, given the always block.

Not sure what other source to get it from.  I have reset, and I have a 
way to generate a soft_reset signal (currently, the always block).

I guess I could put the reset signal into a delay, something like:

// set reset_en from always block
  always (@posedge clock) {
     reset <=                     (reset_en ? 0 : 1'bz);  // if you can 
do that sort of thing in Verilog
     reset_in <=               (reset_en ? 0 : !reset)

So, the trigger of reset going low will happen 1/2 cycle after we 
request the reset.   Obviously, have to feed it into the IDE and fix 
errors, as I doubt you can create reset as a reg when it is an inout.  I 
assume you'd need to create a registered signal, and then assign reset 
to the value.

Asking for a soft reset that does not reset the internal PLD registers 
is a pretty common thing, so I probably ought to get this right and then 
consider the resulting code the "cookbook" example.

> -Nate
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Jim Brain

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Received on 2015-09-10 06:01:14

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