On 9/9/2015 11:52 PM, Nate Lawson wrote: >> On Sep 9, 2015, at 7:54 PM, Jim Brain <email@example.com> wrote: >> >> It's supposed to allow the reset line to reset the registers, but the soft reset should reset the machine (through the RESET pin) but not reset the registers. Currently, the soft reset is working but it resets the internal register FFs. I supposed that could be a question. The code I received was: >> >> inout reset; >> ... >> reg reset_en = 0; >> always @(negedge clock) reset_en <= (cart_config3_reg_ce & data); >> >> assign reset = (reset_en ? 0 : 1'bz); // if we trigger soft reset, set reset line to 0, otherwise hiZ >> assign reset_in = (reset_en ? 0 : !reset); //if soft reset, 0, otherwise !reset >> >> And then the registers are: >> >> register #(.WIDTH(6)) cart_config1_reg(clock, reset_in, cart_config1_reg_ce, data[5:0], cart_config1); // active high reset. > I don’t quite know what your intended behavior is just from the above, but I can tell you what it does: > > If “data" (register?) bit 7 is set and so is config reg 3 bit CE, reset_en goes high on falling clock edge. This enables two muxes, “reset” and “reset_in” (bus line or register?) reset is the reset line from the VIC-20, data is the VIC-20 data bus, and config_reg3_ce = !io2 & address[12:0] = $1f2 & !r_w (so, IO2, $1f3 address, write) reset_in is not a register, just an assign, I just checked. I can define it as a wire, but it seems Verilog assumes that much. > > “reset” outputs HiZ by default but drives a low value when “reset_en” goes high. Since this is type inout, I assume it resets the machine via an external pin. Yes. > > “reset_in” drives the inverted value of “reset” by default, but also drives a low value to the config reg when “reset_en” goes high. It drives reset on your config registers. Yep. > > The weird part to me is that “reset” doesn’t appear to be registered, yet the inverted value is passed to reset_in by default. So it starts by driving the inverse of HiZ (which is undefined, bad) Maybe since you now know reset is the VIC-20 reset line that clears things up. > by default before “reset_en” goes active. But since “reset” is not registered but both are triggered by “reset_en”, it seems like there’s an undefined region during that change where “reset_in” could be driving the inverse of 0 (1 or active high). That’s probably what resets your config register. > > If you tell me what you want this to do, I can suggest how to fix. As noted previously: "It's supposed to allow the reset line to reset the registers, but the soft reset should reset the machine (through the RESET pin) but not reset the registers. " So, if someone sends $80 to $99f2 (I think), the machine should reset but the registers should not. the VIC-20 reset line is on the CPLD as "reset". That way, folks could set up the banks they want, hide the registers (if desired), and then hit the soft reset functionality to start the machine up again with the right memory config. Jim Message was sent through the cbm-hackers mailing listReceived on 2015-09-10 06:00:07
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