Re: final cartridge for vic 20

From: Jim Brain <>
Date: Wed, 9 Sep 2015 21:54:04 -0500
Message-ID: <>
On 9/9/2015 12:53 PM, Nate Lawson wrote:
> If you have any questions, feel free to post it. Depending on the CPLD type you’re using, you can often restructure equations to take advantage of the cell structure and combine multiple terms into a single one.
> -Nate
>> On Sep 9, 2015, at 10:19 AM, Jim Brain <> wrote:
>> I worked a bit on the Verilog last night.
>> As usual, running out of macrocells on the CPLD, but the registers I have right now are:
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Well, I don't know that I have questions, but I am happy to put my 
Verilog somewhere for people to comment on.  I am using Xilinx XL series 
(xc95144xl specifically).  It all fits currently, thought it uses 
132/144 macrocells, and I still should add in:

debounce for 1 or 2 switches on the unit.
better reset code (the soft reset is some code someone gave me from, but it does work as expected.  It's supposed to allow the 
reset line to reset the registers, but the soft reset should reset the 
machine (through the RESET pin) but not reset the registers. Currently, 
the soft reset is working but it resets the internal register FFs.  I 
supposed that could be a question.  The code I received was:

inout reset;
reg reset_en = 0;
always @(negedge clock) reset_en <= (cart_config3_reg_ce & data[7]);

assign reset    =                (reset_en ? 0 : 1'bz); // if we trigger 
soft reset, set reset line to 0, otherwise hiZ
assign reset_in =                (reset_en ? 0 : !reset); //if soft 
reset, 0, otherwise !reset

And then the registers are:

register #(.WIDTH(6))                cart_config1_reg(clock, reset_in, 
cart_config1_reg_ce, data[5:0], cart_config1);  // active high reset.


Jim Brain

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Received on 2015-09-10 03:00:07

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