On 9/9/2015 8:38 AM, Marko Mäkelä wrote: > On Tue, Sep 08, 2015 at 01:05:58PM -0700, Terry Raymond wrote: >> So Im looking forward to Jim's product. I have a NTSC Vic-20 and >> enjoy it. > > FWIW, my menu software auto-detects PAL/NTSC and shows a nice > timer/raster-interrupt-driven "cursor" across the screen. :) I have > one bare NTSC board, so I can test it. Too bad my "smart" TV is not > smart enough to display the picture, while my old PAL CRTs are dumb > enough to display it, iirc black&white though. :) > > This week, I am really busy with $work deadlines. > > Next week, I will try to look at patching VICE -cartfp for Jim's > register layout, so that I can start porting my menu to it, as a > proof-of-concept, so that Jim can test it with the real hardware. > > I guess we could set up a github project for this? I still use > Subversion for private stuff, but at work we recently switched to git. > > Marko > > Message was sent through the cbm-hackers mailing list I worked a bit on the Verilog last night. As usual, running out of macrocells on the CPLD, but the registers I have right now are: config1 (ram, io2, and io3 configs, 2 bits each, 6 bits of data) config2 (blk1,2,3,5 configs, 8 bits total) config3 (2 switches and LED, bit to disable registers and bit to soft reset (4 bits) reserved (always 0) ram bank lo (8 bits) ram hi (2 bits, others read as 0) io lo io hi blk1 lo blk1 hi blk2 lo and hi blk3 lo and hi blk5 lo and hi That is 16 register locations, and I am putting them at the top of IO2 ($9bfX, I think) It is unclear if stuffing the high order bank bits into a smaller number of registers helps with macrocell count but I will try it. Jim -- Jim Brain email@example.com www.jbrain.com Message was sent through the cbm-hackers mailing listReceived on 2015-09-09 18:00:07
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