Re: final cartridge for vic 20

From: Jim Brain <>
Date: Sun, 6 Sep 2015 15:55:40 -0500
Message-ID: <>
On 9/6/2015 2:24 PM, Marko Mäkelä wrote:
> On Sun, Sep 06, 2015 at 01:50:06AM -0500, Jim Brain wrote:
>> It does.  Though I have not set the register map in stone, the config 
>> is as follows:
>>    Config 1:
>>    0-1: RAM Config (00 = absent, 01 = ROM, 10 = RAM R/W, 11 = RAM RO)
>>    3:2: RAM high bank
> I do not get these.
Let me know if they are stil unclear.  This is just the config and high 
order bank bits for the RAM1/2/3 chunk of memory space.
> I think it would be simplest to let the processor copy the data from 
> flash to RAM, mapping the flash only at BLK5. If you have spare 
> capacity on the chip, implement a DMA controller that does the 
> copying. :)
The HW allows one to only map ROM at BLK5, but I wanted the HW to 
support as many configs as possible.  Some games want to be mapped at 
BLK3 and BLK5, and BLK1 and 2 are easy to replicate.  If I want to map 
RAM there, I need the bank registers, and then adding support for ROM at 
any of the locations is just a tweak to the CE line.

As for DMA controller, still learning HDL :-)
> I see, you are using the bank register for both RAM and flash bank. 
> With RAM, the high-order bit of each register would be unused.
> Sounds good, it could be used by some KERNAL extensions, such as the 
> file system driver that I proposed.
That was the idea in the request.  Evidently MEGA CART does this and 
hides SJIFFYDOS in that area.
> The register layout would be easy to change by patching the VICE 
> source code as well. I think I would prefer to do that.
And that is fine.  I am torn between two options:

0 config1 (3 2-bit configs for RAM,IO2,IO3 + ability to hide registers 
until reset and soft reset bit = 8 bits)
1 config2 (4 2-bit configs for BLK1,2,3,5)
2 bank_RAM_lo
3 bank_RAM_hi
4 bank_IO2_lo
5 bank_IO2_hi
6 bank_IO3_lo
7 bank_IO3_hi
8 bank_BLK1_lo
9 bank_BLK1_hi
A bank_BLK2_lo
B bank_BLK2_hi
C bank_BLK3_lo
D bank_BLK3_hi
E bank_BLK5_lo
F bank_BLK5_hi


0 config and bank:  rrr:cc:bbb (rrr = which bank to set/read, cc = 
config, bbb = high order bits of bank, using bank 7 as way to sneak in 
bits for reset and register hiding)
1: bank:  aaaaaaaa (low byte of bank reg)

The former is easier to implement on CPLD, but the latter might be 
easier for programmers (don't know).  The former seems more in "keeping" 
with the register layouts of the rest of the ICs, but might not be 
seeing everything.

Jim Brain

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Received on 2015-09-06 21:00:07

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