On 9/6/2015 12:59 AM, Marko MÃ¤kelÃ¤ wrote: > Hi Jim, > > > This sounds very much like my 3-chip Vic Flash Plugin > http://www.iki.fi/~msmakela/8bit/vfp/ which never went beyond the > prototype stage, with the exception that we only used a 4MB flash and > 32kB SRAM. With more flash and SRAM, you would probably not want to > bother with any compression at all (which I did bother with, because > the original version only had 512k flash). Yes, I have an older email response from you in response to didier where you talked about your design. I was hoping to use some of the SW source you created. > > I would love to contribute to this. I can send any or all parts of it. > > The default configuration of the CPLD should map one 8kB page of the > flash to BLK5 when the system is reset. The menu software (or the > bootloader of it) would live there. It does. Though I have not set the register map in stone, the config is as follows: Config 1: 0-1: RAM Config (00 = absent, 01 = ROM, 10 = RAM R/W, 11 = RAM RO) 3:2: RAM high bank 4: 0 5: 0 6: 0 7: reset unit - write only (does not currently save register values, which it should, so I am looking at my Verilog) Config 2: 1-0: BLK1 Config (00 = absent, 01 = ROM, 10 = RAM R/W, 11 = RAM RO) $2000 3-2: BLK2 Config (00 = absent, 01 = ROM, 10 = RAM R/W, 11 = RAM RO) $4000 5-4: BLK3 Config (00 = absent, 01 = ROM, 10 = RAM R/W, 11 = RAM RO) $6000 7-6: BLK5 Config (00 = absent, 01 = ROM, 10 = RAM R/W, 11 = RAM RO) $a000 // default is BLK5 ROM enabled. Bank Hi Reg: 1-0: BLK1 high order bank bits 3-2: BLK2 high order bank bits 5-4: BLK3 high order bank bits 7-6: BLK5 high order bank bits RAM1/2/3 Bank Reg 7:0 BLK1 BLk2 BLK3 BLK5 > > I found the Vic Flash Plugin register map in the source code. > > bankreg = $9800 ; ROM bank switching register (A20..A13, default value > $00) > cfgreg = $9801 ; configuration register (default value $40) > ;; b7 == 1 => I/O2 disabled until RESET > ;; b6 == 1 => BLK5 write protect (default) > ;; b5 == 1 => RAM at BLK5 (instead of ROM) > ;; b4 => 0=3k (RAM1-3), 1=8k (BLK1) > ;; b3 == 1 => master RAM enable (BLK2,BLK3 is always enabled) > ;; b0 => A21 Well, I might be able to support this register mapping, but it does differ somewhat from the current one I am using. I was able to test that all of the Verilog is working fine, and I can map ROM and RAM and R/O RAM into each BLK, and either put different banks or the same bank into multiple BLKs. The initial register set can support all of the above functionality, but I have had a request to offer a way to map RAM into IO2 and IO3 for extra capability, so I am considering how I might do that in the same way (adding them individually requires 3 more registers, which I can do, but then I'm at 11 registers, and I was hoping for a binary value. I am considering doing something like: reg0: config: aaaa:bbcc aaaa = memory map location: 0000 = RAM1/2/3 0001 = BLK1 0010 = BLK2 0011 = BLK3 0100 = BLK5 0101 = IO2 0110 = IO3 bb: nothing at present. cc = config: 00 = absent 01 = ROM 10 = RO RAM 11 = RW RAM reg1: 7:0 low order bits of bank reg2: 7:0 high order bits of bank I could also do 2 config registers for 2 bits per slots (14 bits of data needed), and then 14 registers (low/high bank registers for the 7 memory banks.). This is probably the easiest to implement. My only concern: I doubt there would ever be a need for more than 12 bits per bank register (4096 8192byte banks, or 32MB of FLASH or RAM), so using a whole register for a high bank seems overkill. Right now, only 2 bits are needed per bank hi register. > > While I have not spent any time on C= stuff in the past, I would love > to participate in this project. I think that the first step would be > that you modify VICE so that it emulates the new hardware. I'm happy to obtain help. Well, since I have the prototype right here and I can test with the real hardware, VICE is not as much a need for me. As you can see, still trying to decide what register layout makes the most sense from a programming point of view. > > I hope someone has usable 6502 file system code. Given that the flash > is only 8MB, it could be mapped to something like 128 tracks with 256 > sectors each, in a 1541-style layout. Thomas Giesel's (sp?) EasyFlash already contains a 6502 FLASH ROM programming code, so it should be easy to adapt. Hppy to send a unit for development. It is a Xilinx XC95144XL, MX29LV640 and AS6C8008 on the card. ISE WebPack would be useful to modify the CPLD. Message was sent through the cbm-hackers mailing listReceived on 2015-09-06 07:00:51
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