IEEE drive CPU inter-communication

Good morning gentlemen,

Does anyone have any information which describes the basics of the 
processor inter-communication on the IEEE drives? I know the two cpu's 
operate out of phase, and that they share access to some common areas of 
RAM, but it is not clear how tasks are handed off from the DOS 
controller, status receieved etc.

I ask because I'm working on resurecting the 8280 I received a few 
months back. There are RAM issues on the DOS board which are proving 
tricky to isolate and I wanted to take the drive controller CPU out of 
the equation. Removing the second CPU renders the board completely 
inoperable; I assume because a number of signals are left floating.

Any guidance greatly appreciated,

Rob.

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