Re: CBM720 heads up

From: A. Fachat <>
Date: Sun, 23 Nov 2014 18:21:42 +0100
Message-ID: <2256148.Y5i8HTH1n8@euler>
Hi there,

On Sunday 02 November 2014 02:03:55 you wrote:
> > Unfortunately IEEE488 does not work (at least with my Arduino XD2031
> > setup... which probably doesn't mean much)
> Check the CIA and TPI chips then.

Unfortunately I found that it didn't even get to using the IEEE bus because of 
memory problems. 

It looked as if in Bank 1 Bit D5 would be flakey. Writing various patterns to 
it suggested that when you write a 0 to it, it would not be stable. Address 
patterns are located in various 256 byte pages of bank 1, but there in the top 
areas under addresses 127 and 255 of each page.

Unfortunately replacing the corresponding memory chip did not help - same 
error pattern with a new chip. 

So what do you think it could be?
- "bank 1" is NOT what uses "/CASSEG1,RASSEG1" in the schematics? then I have 
replaced the wrong chip (from the wrong bank)
- I think the data bus buffer U33 is highly unlikely. It buffers all DRAM 
accesses and the error is specifically located
- One of the four 4-to-1 selectors U27,U28,U34,U35? Bit patterns of the error 
would then suggest multiple of those
- MUX decoding for those selectors? would that not influence all addresses?
- Or the PLA U75 in the end which is supposedly known to fail? It creates 
/CASSEG1,/RASSEG1. But why then only some of the addresses within the bank? 

I'm baffled.

(see also )

Any help appreciated!

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Received on 2014-11-23 18:00:03

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