I think I misinterpreted the first measurements. Because of the indirect indexed access ($11),Y there were two accesses. In the first measurement I only saw the first read but interpreted it as the write access. I found that out when I later checked the r/-w line. So no bus conflict. André Am 31. August 2014 18:39:58 schrieb Gerrit Heitsch <email@example.com>: > On 08/31/2014 05:51 PM, A. Fachat wrote: > > On Sunday 31 August 2014 16:14:34 you wrote: > >> Hi, > >> > >> So if it is not the RAM, what could happen in the driver - probably UE9 or > >> UE10 here > >> http://www.zimmers.net/anonftp/pub/cbm/schematics/computers/pet/univ/8032081 > >> -05.gif that causes this? Probably a slight delay in switching the line on > >> or off? > > > > Nope. Got it. It in fact was the RAM itself. > > > > Replaced the UE9 and UE10 74LS244 buffers to no avail, still not full memory. > > > > Then replaced the UA16 RAM - there you go, full memory! > > Learn something new every day... I didn't think that a 4116 DRAM would > be able to 'win' against an LS-TTL driver. > > Gerrit > > > > Message was sent through the cbm-hackers mailing list Message was sent through the cbm-hackers mailing listReceived on 2014-08-31 18:00:02
Archive generated by hypermail 2.2.0.