On 7/20/2014 7:06 PM, silverdr@wfmh.org.pl wrote: > On 2014-07-17 at 22:44:32, silverdr@wfmh.org.pl (silverdr@wfmh.org.pl) wrote: > >>> I've got all the details from Jim, including schematic and the code. I'll prepare it >>> and put online soon. >> > http://e4aws.silverdr.com/hacks/6500_1/ > > Fully online. > > Thanks big time to all who contributed! > -- > SD! > > Message was sent through the cbm-hackers mailing list I need to make an update to the code, and your page: "Gerrit Heitsch, modified based on empirical testing. Once synchronization happens, it loads one memory location into the .A register, sends the opcodes to store it to PORTA, and then drops out of TEST mode during the cycle when the store will actually happen. It then JAMs the CPU, reads the data from PORTA, sends it to the UART, and repeats the process, using a new memory location. " Is a bit incorrect. It should be: "Gerrit Heitsch, modified based on empirical testing. Once synchronization happens, it instructs the internal CPU to load one memory location into the .A register, dropping out of TEST during the cycle when the load from ROM occurs. It then stores the data to PORTA, JAMS the CPU, and the AVR reads the data from PORTA, sends it out via the AVR UART, and then repeats the process for the next memory location." Feel free to update the verbiage int the source. Jim -- Jim Brain brain@jbrain.com www.jbrain.com Message was sent through the cbm-hackers mailing listReceived on 2014-07-21 04:00:02
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