On 07/20/2014 08:02 AM, Jim Brain wrote: > On 7/19/2014 10:36 AM, email@example.com wrote: >> But inside the "loader" code loop you have two additional toggles >> between TEST and NORMAL mode with "extra cycle" inbetween. What was >> this needed for? If I understand correctly - the 6500 should be able >> to *store* to its RAM while running in TEST mode, shouldn't it? > The extra cycle is the dummy cycle when the sta actually happens. I > took the TEST_OFF and TEST_ON out of the code, it stopped working. > > I can't say for certain, but it would seem like only registers can be > written when test mode is high. > > That seems strange. Or we have a phase shift between what you assume internal clock to be and what it really is. Then it could happen that you turn off TEST mode just in time for an opcode fetch you assume has already taken place. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2014-07-20 10:00:02
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