Re: ROM Dump of Amiga Keyboard controller

From: Gerrit Heitsch <>
Date: Fri, 18 Jul 2014 20:41:16 +0200
Message-ID: <>
On 07/18/2014 08:26 PM, wrote:
> On 2014-07-05 at 21:13:22, ( wrote:
>> On 2014-07-05 at 21:11:09, Gerrit Heitsch ( wrote:
>>> Would it be possible to post your code, setup and notes somewhere so
>>> whoever has a spare 6570-036 or other Amiga keyboard controller can use
>>> that info to try to dump it?
>>> My experience with AVR is limited to the ATtiny series and even there
>>> quite limited, but I bet someone else would be able to replicate your
>>> setup easily.
>> I've got all the details from Jim, including schematic and the code. I'll prepare it and
>> put online soon.
> Gerrit, could you be so kind as to return for a moment to the clock phase subject and elaborate a little what was it that we were worried about?

Well, the thing is, the 6502 has no 1 Byte / 1 Cycle opcode. Even 1 byte 
opcodes take at least 2 cycles.

Now, the problem is, when you start feeding bytes to the 6502 via Port 
C, you have to find a way to sync your supplied commands to the 
execution in the 6502.

You can't do that with a string of $EA (NOP) since that takes 2 cycles 
and you can run into the following:


  ex -- ex -- ex -- ex -- ex

ex = executed
-- = Byte loaded as Operand or dummy cycle.

So you never reach the A9 and load the Accu with #$00.

To remedy that you need a command sequence that makes sure a certain 
Byte WILL be executed as a command, from then on you know the internal 
state of the CPU and it becomes easy. That's what I supplied with the 
BIT command. Since with a long enough sequence of NOPs, there are only 2 
alternatives, it will be either the first or the second:

EA EA EA EA 24 EA EA A9 00

ex -- ex -- ex -- -- ex --

-- ex -- ex -- ex -- ex --

Either way, A9 will be executed as command and the accu will be loaded 
with #$00.

The other thing I remember was that the 6500/1 does divide the 
externally supplied clock by two. But the longer I think about it, the 
less I see that as a problem as long as you feed the bytes at the right 
speed (meaning half the clockspeed), the clock phase is of no 
consequence as long as the data read by the CPU is stable the moment 
it's sampled.


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Received on 2014-07-18 19:01:13

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