On 06/30/2014 09:36 AM, Jim Brain wrote: > OK, test bench is running > > 6500 PORTC is wired to AVR ATMEGA32 PORTC > 6500 PORTD is wired to AVR ATMEGA32 PORTB > 250kHz CLK is on PD7 > RESET (active high) is on PD6 > TEST MODE (active low) is on PD5 > > I checked all of the voltages on RESET, and I can send 0,5,and 10V, +- .5V > > Now, I just need some code to try... Well, lets see... For a test we want to set Port D to a pattern. The ports in the 6500/1 don't have data direction registers, they behave like the 6529, to use them as input, just set the bits to 1 and read back. To use as output, just write whatever you want to see on the pins into the output register. So the code would be: SEI ; Make sure no IRQ gets in the way LDA #$55 ; load #%01010101 STA $83 ; store to Port D HLT ($02, stops the CPU to keep the port stable for easy checking) The byte sequence for that is: 78 A9 55 85 83 xx 02 'xx' can be whatever you want since that's the cycle used by the 6502 to actually write the byte to $83. Now we still need to sync up. Lets try this: EA EA EA EA EA EA EA EA EA EA 2C 24 EA xx 78 A9 55 85 83 xx 02 The leading NOPs are just to be sure that even the longest command is done. Depending on where we end up in the sequence 2C 24 EA it will be read by the 6502 either as: BIT $EA24 (3 Bytes, 4 Cycles) BIT $EA (2 Bytes, 3 Cycles) NOP (1 Byte, 2 Cycles) So no matter on what part of that 3 byte sequence we end up, we'll be in sync with the code once we skip the byte following the EA. It might be possible to skip the 2C, but for a first test I decided to be paranoid. Hope this works, the idea came up while I was out for a walk. Remember that the clock you supply to the 6500/1 is divded by 2 before reaching the CPU core. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2014-06-30 18:00:03
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