On Tue, Jun 10, 2014 at 09:05:26PM +0200, Gerrit Heitsch wrote: >You would have to pad the loader with $EA at the beginning, but since >you don't have to deal with addresses and can ignore the program >counter, only have feed the port the right byte at the right time, you >can have as many $EA as you like at the beginning. Even the reset >vector can be $EAEA without causing trouble. I think that it would be a better idea to use a 2-byte 2-cycle instruction that would self-synchronize. When padding with a 1-byte 2-cycle instruction like $EA, you would not know which fetch is for the opcode and which one is a wasted cycle. If you started padding with $A9EA, the RESET vector would be either $A9EA or $EAA9, which are both fine. If the CPU starts executing "in the middle" from $EA, it would unfortunately remain in that mode, because the $A9 would be a wasted fetch, and the next instruction would be $EA again. So, the 2-byte 2-cycle instruction should be such that the 2nd byte is a 3-cycle instruction, say PHA ($48). If all reads would be served via port C, then I suppose that both $A948 and $48A9 would be valid RESET vectors. If the execution started at the $48 byte, the next 2 bytes ($A9 $48) would be ignored by the instruction decoder, and the next instructions would be LDA#$48 ($A9 $48) all over. If the execution starts at $A9, we would already be in sync. I guess that the minimum amount of $A9 $48 padding would be some 5 or 6 complete copies (10 or 12 clock cycles), but it would not hurt to have a very large amount of it. The RESET sequence takes 7 cycles just like any interrupt, right? Did the visual6502.org folks document this? Marko Message was sent through the cbm-hackers mailing listReceived on 2014-06-10 21:00:03
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