On 04/25/2014 04:46 PM, John McKenna wrote: > > From: email@example.com > > > > according to jens schönfeld its a setup-and-hold timing violation. > > > > Yes, but why? The CPU was done with its part of the cycle a few hundred > > nanoseconds before this problem happens. What can the CPU do to VIC > > there that will only surface that much later? > > The CPU doesn't do anything to VIC, at least not in that way. VIC does > it to itself. I forget the exact details, but it involves VIC changing > its mind about what address to put on the bus while /RAS is falling. > The address is supposed to be stable at this point. Yes, but this only happens when you exploit one of the undocumented features of VIC to produce visual effects. And for that, the CPU has to write values to certain registers. During normal (boring) operation this problem never happens. > The only part the CPU plays is to write to a register, which triggers > DMA at the wrong time. Yes, but why exactly? The CPU has handed the value (whatever it is) to the register hundreds of ns before VIC puts his addresses on the bus. Everything should be stable by then. Why isn't it? And this only happens on some VICs, others don't have that problem. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2014-04-25 15:02:09
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