On 03/09/2014 09:11 PM, smf wrote: >> Well, TED does it and it works. > > The 6566 was designed while they were waiting for fast enough drams to > use, the 6567 was then hacked so they could get the c64 out of the door. Well, Commodore did already have experience with DRAM controllers in the CBM series and they also had fast enough DRAMs (16KBit) to use, just not big enough DRAMs (64KBit) that were affordable. > There is no real way of determining why they did what they did & it's so > long ago their recollection is likely to be incorrect. I did some pin counting and VIC doesn't have enough pins to allow non-multiplexed addresses while still supplying the DRAM control signals, even if limited to 14 address lines (16KB). They likely didn't want to go to 48pin DIP if they could make it work with a rather weird multiplexed/non-multiplexed mix. This way VIC does all of the DRAM control and the extra logic needed is the 74LS258 and the 74LS373. And the PLA to gate _CAS, of course, since VIC just generates _RAS and _CAS twice per PHI0 cycle. I would expect the main differences between the 6566 and the 6567/69 to be the address bus logic with the multiplexers, additional stuff in the timing generator (for _RAS and _CAS signals), the 8Bit-refresh counter the 6566 shouldn't have and a little bit of glue logic to make it work together. Compared to the vast arrays of sprite logic on the die, not really much. > With TED they had the benefit of hindsight and were able to work with > dram manufacturers during the design process. It also wasn't designed > for speed (no sprite dma needed and an additional bad line for colour > fetches from dram etc). You sure about them working with DRAM makers? The DRAM cycle looks the same as with VIC to me and with the relaxed timing (around 500ns for the whole cycle on VIC and TED) you don't need any special tricks to make it work reliably, even with cheap 200ns DRAM. So you can just use most of the circuit from VIC with only minor changes. > FWIW the Amiga 1000 ended up using the same scheme as the C64, so agnus > only controlled it's own access to chip ram. The fat agnus designed for > the a500 had the motherboard multiplexers integrated so it controls all > access. I think the main reason was, again, pincount. Compared to the complexity of AGNUS, adding the multiplexers and support logic wouldn't have added much to the die, but a lot more pins to the chip (48pin DIP => 84pin PLCC). Gerrit Message was sent through the cbm-hackers mailing listReceived on 2014-03-10 12:00:04
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