Re: More CPLD explorations

From: Gerrit Heitsch <>
Date: Sat, 01 Mar 2014 22:51:03 +0100
Message-ID: <>
On 03/01/2014 10:41 PM, Nate Lawson wrote:
> On Feb 27, 2014, at 4:54 AM, Gerrit Heitsch <> wrote:
>> On 02/27/2014 08:35 AM, Nate Lawson wrote:
>>> On Feb 26, 2014, at 8:13 AM, Gerrit Heitsch <> wrote:
>>>> On 02/25/2014 09:44 PM, wrote:
>>>>> On 2014-02-25 at 20:49:07, Gerrit Heitsch ( wrote:
>>>>>> The fun part is, if you look at a chip itself and measure just between
>>>>>> +5V and GND of that chip, everything is a bit noisy, but not really
>>>>>> bad.
>>>>>> It's just that the ends of the board in relation to each other do
>>>>>> funny
>>>>>> things. The 1V peak-to-peak is only a few ns, and a half cycle is
>>>>>> about 500ns.
>>>>> Well, this doesn’t mean such thing can be “written off” due to the length of the pulses. Of course it depends on various things but it still can be a disruptive factor for regular operations even if those are short.
>>>> Also, remember, the image I mailed you shows the difference in GND potential between the 2 points far away from each other. When you take a closer look at Vcc and GND on each IC, it's still noisy, but a lot less so.
>>> Sounds like ground bounce, possibly solvable by finding the responsible line drivers and providing decoupling caps.
>> It's most pronounced when _CAS goes low. The only IC that will have the bus at that point are the DRAMs, VIC and CPU. Also, it doesn't happen on every _CAS cycle which suggests to me it only happens during a read cycle, suggesting the DRAMs are to blame. Probably turning on their output drivers?
>> The problem is still present on the 250466, the first C64 board with the 64Kx4 DRAMs. There, the measurement was taken between the metal bracket at the Expansion port and pin 12 of the BASIC ROM. I had _CAS on one channel (2V/square) and the ground on the other (500mV/square). Horizontal was set to 100ns/square.
>> Replacing the 2 DRAMs with my SRAM-Adapter (using an Alliance AS6C1008-55 plus some glue logic and decoupling caps) makes it less pronounced, but it's still there, maybe a few ns later than with DRAM.
>> The DRAMs on the C64 board already have their decoupling caps (100nF), but it's interesting that the C16, Plus/4 and C128 use 220nF caps for the RAMs while everything else stays at 100nF.
> I don’t know the bus timing of the CPU/VIC DRAM access and haven’t seen your scope trace, but perhaps it’s related to a switch between the two between clock phases. You wouldn’t see it on every _CAS cycle if the combination of addresses being accessed were both in the same column, but it might be related to the Hamming distance of addresses.

Every PHI0-cylce contains 2 full DRAM cycles, one for VIC and one for 
the CPU. The CPU gets the bus while PHI0 is HIGH. Every DRAM cycle is a 
complete RAS/CAS cycle. _CAS goes low almost in the middle of a half 
cycle, so there are no changes in the clock signal at that point.

I can mail you the scope trace if you want. Ok, it would be 2 traces, 
one showing _CAS in relation to PHI0 and one showing _CAS with the GND 


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Received on 2014-03-01 22:01:19

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