On 2013-12-17, at 20:35, Gerrit Heitsch <gerrit@laosinh.s.bawue.de> wrote: >> Those I have don’t, but as Gerrit corrected me - it makes sense: there was no intertwining on the original PATA (typical PC crap engineering - like with most PC stuff when compared to the rest..) > > Gets even better. There were even IDE-Cards that omitted the 74LS245 buffers between the ISA slot and the IDE connector. That means that the data bus from the ISA slot was directly connected to the HD over a 40wire cable with no shielding between the signals whatsoever. > > > The funny thing was, it usually worked. Like almost everything PC for about two decades - it mostly, usually worked ;-) At least I believe the other end was not connected directly to the CPU pins like in the SX? > As for the SX-64... Adding length to an unbuffered, non-terminated data and address bus doesn't help with the signal quality. And if you ever looked at the signals in a C64, you know they are not very clean to begin with. True, true.. I didn’t sample all on all boards but when I was debugging that ROM replacement, I had a chance to see some of it. > I sometimes wonder if one could improve stability if one removed the pullups for A12 to A15 and replaced them with a 74LS125. The inputs connected to +5V, the enable signals to AEC. That way A12 to A15 would no longer slowly float up to +5V when VIC takes over the bus but get pulled HIGH quickly. Maybe the same for R/_W. BTW - I wondered why is it done like that in the first place? I mean the address lines, not R/_W. > Another detail I'd take a closer look at would be the 7406/pullup combo that tristates the output the 74LS257 multiplexers when it's VIC's turn. Replace it with a real driver (74LS04). That “nice” 180 on the OC output. Right - another interesting idea. It was probably a good (read: cheaper) solution and a good use for the otherwise unused 7406 gate. -- SD! Message was sent through the cbm-hackers mailing listReceived on 2013-12-17 21:01:59
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