RE: C64 DMA

From: COPLIN, Nicholas. (ncoplin_at_orbeng.com.au)
Date: 1999-11-25 06:30:19

An update for those interested:

I've tracked down a 32bit assembler base core 6502 emulator.  Claim
according to the information files is that it runs 15-16Mhz on a P60, there
for should be 25Mhz on a P100 - pretty flashy.

Problem is I've not been able to compile effective following the author's
instructions, despite his gracious help. Code originally based for  NASM and
Watcom C, but of which I've borrowed copies of but with no success.  Is
anybody else willing to give it a try?

Regards, Nick

> -----Original Message-----
> From:	COPLIN, Nicholas. [SMTP:ncoplin@orbeng.com.au]
> Sent:	Friday, 19 November 1999 9:35
> To:	'cbm-hackers@dot.tcm.hut.fi'
> Subject:	RE: C64 DMA
> 
> Thanks for the information so far....
> 
> I downloaded a few core 6502 emulator codes yesterday and compiled to see
> if
> its all worth while.... C-only coding examples give ~3Mhz emulation on a
> P100 - probably not enough benefit to justify the pain... so will have to
> find/code an assembler core... internet searching sounds easier than
> coding... in my mind need 20Mhz benefit with a P100 (or 486/100) to making
> worth while.....
> 
> I was thinking 8255 as they might save on real estate and the DMA access
> need only be 1MHz (else trouble syncronising....).  Descrete buffers may
> also do the trick....  I was thinking of even being lazier and doing it
> with
> two/three LPT ports (old PC bus is ~7.xxMhz)
> 
> The other thought was to go straight to a 40pin "plug to the 6510 socket"
> and thus not have to worry about port 0000/0001 and D000-DFFF area.....
> mmm.... 1Mhz comms along a 30cm ribbon cable?!?!?
> 
> Step 1 i think is to identify the core emulator's speed.
> 
> - Nick
> 
> > -----Original Message-----
> > From:	Marko Mäkelä [SMTP:msmakela@cc.hut.fi]
> > Sent:	Thursday, 18 November 1999 22:27
> > To:	cbm-hackers@dot.tcm.hut.fi
> > Subject:	RE: C64 DMA
> > 
> > On Thu, 18 Nov 1999 g.j.p.a.a.baltissen@kader.hobby.nl wrote:
> > 
> > > The make sure evrything goes smooth, you put some NOPs behind the
> > > instruction in case the timing is not quit right.
> > 
> > I have never understood this.  I've seen unnecessary NOPs in the bank
> > switching code of cartridges and in some other places.  It is hard to
> > believe that there could exist a latch having a long enough propagation
> > delay (over 300 ns) for an approach without any NOPs to fail.
> > 
> > > The Z80 starts at $0000, its reset-address, the first time it is
> > > activated. The rest is the same as with the 6510.
> > 
> > According to the Programmer's Reference Guide, in the Commodore CP/M
> > cartridge, the Z80 addresses do not directly correspond to 6510
> addresses.
> > I think it was off by $1000 ($1000 in the C64 memory would be $0000 in
> the
> > Z80 address space).
> > 
> > > I did not completely understand the above.
> > 
> > I did.  He is planning to use the C64 for I/O of another computer system
> > (this is just what accelerator cartridges do).  One Finnish guy asked
> > about this in comp.sys.cbm recently; maybe you could co-operate with
> him?
> > 
> > I think it's quite possible to use the cartridge port for write-only
> > access to all of the RAM (maybe expect $d000-$dfff) and I/O.  By
> default,
> > all other memory areas expect $d000-$dfff are write-through (when you
> > write, the value will go into RAM), and by using the -GAME and -EXROM
> > lines appropriately, you could perhaps be able to enable the RAM at
> > $d000-$dfff for writing.  Add a wire running into the 6510's CHAREN
> > output, if you cannot figure out any better solution.
> > 
> > 	Marko
> > 
> > -
> > This message was sent through the cbm-hackers mailing list.
> > To unsubscribe: echo unsubscribe | mail
> > cbm-hackers-request@dot.tcm.hut.fi.
> 
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