On Dec 13, 2013, at 9:39 PM, Jim Brain wrote: > wire [1:0] divisor; // Why does this need a wire def, when isCLK16 does not, and they are both used as inputs to registers? > … > assign isCLK16 = (data[3:0] == 0); > assign divisor = (ebps_reg_en & mode ? data[1:0] : 0); I believe it's because divisor is multiple lines (an array of wires), not just a single wire. I recommend Ciletti's book on Verilog for a clear but also in-depth approach to digital design. The latest version is really expensive still: http://www.amazon.com/Advanced-Digital-Design-Verilog-HDL/dp/0136019285/ The previous edition (which I have) is cheaper: http://www.amazon.com/Advanced-Digital-Verilog-Ciletti-Hardcover/dp/B008CMLQT2/ Also, Amazon mislabeling by sellers means you could take a chance on this one ($30), although it is unclear what edition it is: http://www.amazon.com/Advanced-Digital-Design-Verilog-HDL/dp/0132465574/ -Nate Message was sent through the cbm-hackers mailing listReceived on 2013-12-14 21:02:14
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