On 12/12/2013 11:39 AM, Gerrit Heitsch wrote: > On 12/12/2013 06:31 PM, brain@jbrain.com wrote: > >> So, I thought about a CPLD solution that would "massage" the 6551 >> registers to fit a 16550 or similar device. But, then, I decided if I >> was going to massage an interface, why not massage the interface to a >> uC. That would allow many peripherals to be created. >> So, that's my goal. We'll see how far that goes. I found some Verilog >> for dual port registers, which seems useful. > > Don't forget, that when reading from the 6551-lookalike, you have less > than 500ns (in a C64) to figure out what the 6502 wants and supply the > correct data. Not a problem for the hardware, but if you want to > emulate a 6551 in part with a controller, that's quite tight. My plan was to remove that timing concern by putting the registers in the CPLD. To a large degree, I think one could treat the 6551 interface as a 4 byte dual port RAM. At least registers 1,2,and 3. Register 1 needs a bit of additional logic in that a write to it should reset the registers and cancel any interrupts. Mainly, register 0 is the issue. If you treat it as 2 RAM locations (write only register and read only register, then you only need to deal with the fact that a read from register 0 should return a 0 when no additional byte has been received. So, a read from reg0 should put the value on the databus and a 0 into the register, unless the uC is currently storing a new value into the register. But, if you implement 5 dual port registers, the uC can look at the data at a different time than needing to be involved only in 500uS intervals. The trick is creating 5 lines that indicate when registers have been touched, and resetting those lines when the respective line is read. My main concern is not the registers per se, it's the synchronization, as I understand such things are the "gotchas" of programmable logic. The advantage to such an interface is that it can be used as a general purpose (1 data + 3 config) interface. So, a device could power up as a "6551" but then allow some config line to reconfigure the interface to respond to a different layout (the data path still needs to be on register 0, but the config bits can take on completely new meanings) Maybe emulate the WizNET 4 registers, for example. If the registers were extended to 16, then one could potentially emulate a cs8900 TCP/IP IC, though I know Gideon has been challenged doing that in 1541U2, and I'm not sure of the utility of doing so. As I noted, it's an idea. Now, it's time to hunker down and learn Verilog enough to make it happen and see if succeed or fail. It's probably doomed, but it's a good exercise to try. Jim > > Gerrit > > > > Message was sent through the cbm-hackers mailing list -- Jim Brain brain@jbrain.com www.jbrain.com Message was sent through the cbm-hackers mailing listReceived on 2013-12-12 20:00:59
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