I know it's not much, but I was able to successfully synthesize and use a small chunk of handwritten Verilog last night to implement 4 read/write registers in a CPLD. I wired it up to the C64, and 56832-56835 now can hold 4 different value. Pretty trivial, but it's something. Thanks for the pointers and help. I'm still fighting when to use wire, and when to use reg, when to use always and when to use assign, etc., but I'll sort it out. Interestingly, my code did not work until I set the registers to react on negedge of clock. I implicitly understand (not all of the signals are ready when phi2 goes high), but I have not investigated to see which signals lag phi2. For others that write HDL, is this common with the 64/128? I'm using a -10 part, if that matters. Jim -- Jim Brain email@example.com www.jbrain.com Message was sent through the cbm-hackers mailing listReceived on 2013-12-10 08:00:06
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