Just a couple of clarifications. My reference to the 6522/6526 timers referred to timers restarting, or latches containing data being cleared once read. I was NOT referring to anything sitting on a data buss somewhere affecting their operation. (it's late here, that's my excuse!) Julian Monday, September 9, 2013, 12:07:30 AM, you wrote: > Gerrit, HÁRSFALVI. > Thanks both for your explanations - I'm getting there, I think. > From what I gather: > When a WRITE is written to the TED keyboard latch, during the same 1/2 > cycle that the CPU has the buss (and Data is still valid), the TED > latches the contents of the TED input keyboard port. The actual BYTE > written is not looked at by the TED - it is only used to assert the > appropriate signals on the data buss (in the same way 6522/6526 > timers are (re)started by a read.) Message was sent through the cbm-hackers mailing listReceived on 2013-09-08 15:01:14
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