RE: FPGA/CPLD different approach

From: Bil Herd <>
Date: Tue, 3 Sep 2013 09:15:57 -0400
Message-ID: <>
I did a quick fitting on some opencores and found that the PIOs and
support chips probably fir in the CPLDs and that the processors probably

I have a question for anyone that is interested in using FPGA/CPLD emulated
parts: How important is it that the PCB of a drop in replacement stay
strictly in the foot print of a 40/48 pin chip or is the PCB okay to be
wider than .6 once its .3-.4 above the socket its inserted into?


*From:* [mailto:] *On Behalf Of *Ed Spittles
*Sent:* Tuesday, August 27, 2013 4:13 PM
*Subject:* Re: FPGA/CPLD different approach

For some purposes OHO's GOP board might be a better fit than the GODIL -
it's smaller, got fewer pins, but has a 512kByte SRAM on board..

(For simple designs there are CPLD variations, but as noted that's not big
enough for a 6502-like CPU, or for ROM or RAM.)

As noted elsewhere, these boards have 5V level converters, crystals, and
on-board EEPROM for configuration.



On 27 August 2013 11:34, Ingo Korb <> wrote:

Bil Herd <> writes:

> I have gone through some test fitting but haven't really checked out
> GODIL, for instance can they program the VCC and Ground pins or do
> they have to physically configure?

They can be freely configured using jumpers, but as Didier noted the
pinning of those headers is a bit weird. IIRC the DIL pin alternates
between the left and right side of the header and the other pin
alternates between 5V and GND for each row, so you can select GND and 5V
for any DIL pin by setting the jumper either horizontally or

> I suspect that to keep the cost
> down that the PCB might be wider than the .6" DIP but didnt yet
> research if thats a show stopper.

It's much wider and longer - the board is 33.5 mm x 74.3 mm, the DIL
interface at the bottom appears to be centered. The overall height
including the DIL pins is ~20 mm.


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Received on 2013-09-03 14:00:13

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