Re: Schematic for 80 Column Adapter for C64

From: A. Fachat <>
Date: Sun, 18 Aug 2013 12:33:56 +0200
Message-ID: <275367045.aPA2KuJdXA@euler>
Hi Ruud,

I think the card is using the "transparent addressing mode" (which I though 
was only for Rackwell 6545, but obviously now also for Commodore 6545-1). It 
is similar to how the VDC in the C128 works. Probably Commodore did the 6545-1 
as a step inbetween the original 6545 and the VDC.

The CRTC keeps an address in two registers, and strobes RA4 when it thinks the 
transfer (read or write) should be done (either phi1 or outside the display 
area). The CPU acknowledges it with an access to the (nonexistant) Register 
31, then the CRTC increases this address by one for the next access.
So the CRTC creates the video address, and the timing, but the actual data 
transfer must be done outside the CRTC (as fits with the CRTC philosophy to 
onyl handle the addresses). This is done with the two '374 on the top left 
next to the ROM on the second page of the schematics.

The only problem (or maybe not looking at how how it's implemented in the VDC) 
is that there is no block transfer within video memory in the CRTC, so 
scrolling must be awfully slow.

See more on that mode here:


On Sunday 18 August 2013 12:10:42 wrote:
> > Hallo Bil,
> > Some schematics for some odds and ends, more coming.
> >
> Thank you! I had a look at it and couldn't understand one thing: how
> can I write to the video memory? I'm used to schematics where either
> the the processor can read from/write to the video memory to the
> 6x45 can read from it.
> MA0..13 are outputs of a counter that cannot be set to a certain
> value by the user, that is, AFAIK. If it can, OK, but then I still
> imagine that, for example, clearing a screen is a time consuming
> bussiness.
> I hope that I'm wrong and missed something. I'm looking forward to
> comments!
> --
> Kind regards / Met vriendelijke groet, Ruud Baltissen
>        Message was sent through the cbm-hackers mailing list

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Received on 2013-08-18 11:02:25

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