Re: DD2 & 3

From: silverdr_at_wfmh.org.pl
Date: Wed, 19 Jun 2013 00:14:11 +0200
Message-Id: <32CBD4DA-C1D4-4C72-8902-B2BCBD9F026C@wfmh.org.pl>
On 2013-06-18, at 22:54, Ingo Korb wrote:

>> Jim Drew raised the issue that the 1541 board timing had a problem
>> with fast SRAM, and that 120ns was about the fastest that worked
>> without corruptions.
>> ( http://www.lemon64.com/forum/viewtopic.php?t=41396 )
> 
> I suspect he is wrong about that and/or the control circuit for his RAM
> was badly designed. Two of my 1541s (an older one with PCB 251830 and a
> 1541-II) have no problems accessing a 70ns 62256 SRAM chip.

That adds to my question: how accessing own SRAM chip can be badly influenced by what is there in the remaining areas of the 6502 address space. The way I understand it, what is needed to properly access SRAM (of any speed) in such system is proper processing of clock and r/_w signal from the CPU itself. This should end with timed feeding the SRAM with _CS and R/_W signals but if I build the expansion - it is me who process the signals.. 

Or am I missing something?

-- 
SD!


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