Hello! John McKenna wrote: > While AEC is high, the high address lines are pulled up by RP4. When > AEC goes low, it takes the processor a little time to start driving the > address bus. In this time, the address is $Fxxx and AEC is low, and > that means a KERNAL access. > > An RC filter followed by a schmitt buffer should fix it, as long as > you're careful not to introduce too much delay. I have no room on the PCB to accommodate an additional chip with Schmitt trigger. But I think this would not be necessary. I routed the KERNAL_CS line via a RC filter (R = 3.6 kOhm, C = 5 pF) and ANDed this with original KERNAL_CS line. This makes sure that the resulting signal starts a bit later than original (late enough to bypass the pulses) but ends when the original ends. The Flash now seems happy and responds properly to both reads and writes :-) Regards, Michau. Message was sent through the cbm-hackers mailing listReceived on 2013-06-10 20:05:05
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