On 6/4/2013 12:57 PM, Gerrit Heitsch wrote: > On 06/04/2013 07:23 PM, Jim Brain wrote: >> On 6/4/2013 11:59 AM, Gerrit Heitsch wrote: >>> On 06/04/2013 04:14 AM, Jim Brain wrote: >>>> As I look at it, I can;t help but wonder if some juggling of the >>>> address >>>> lines and such would simplify things and remove the requirement for an >>>> inverter altogether, but I am not seeing an easy way to do it. >>>> >>>> http://jbrain.com/vicug/gallery/vicmidi/VIC_MIDI_Schematic >>> >>> You have a few unused inputs on the LS688. Can't you use them to >>> include PHI2 into the _SEL signal already? That would mean you could >>> free up some inputs on the other logic simplify the circuit there. >> My concern there is that it delays PHI2 all over, and it's typically the >> last signal to switch. I felt putting it through logic would create >> timing hazards. > > That shouldn't be much of an issue with the current logic chips and > become less so if you can reduce the logic further. I'm struggling with that. ahct138 is 12nS worst case, and hct688 is 34nS worst case (@25C) That's over 46nS of delay, not including the ahct14 delay of 8ns for ahct14. 54ns is quite a bit. Doesn't the VIC-I use the other half of the cycle? >>> Then you should read the datasheet for the Flash since for most RAMs, >>> _WE overrides _OE, meaning you can tie _CE and _OE together. If that's >>> the same for the flash, you can free up an inverter for use elsewhere. >> That. I did not know. I will check that tonight. > > Checked the datasheet for a µPD43256 from NEC, as soon as _WE goes > low, _OE becomes 'x' (don't care) 39sf010 datasheet specified !OE must be Vih (High) during write cycle. Jim Message was sent through the cbm-hackers mailing listReceived on 2013-06-04 22:00:03
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