RE: My ColourPET Project

From: Martin Hoffmann-Vetter <>
Date: Thu, 2 May 2013 21:01:22 +0200
Message-ID: <005501ce4767$709f3a50$>
Hello Steve,

> I see that both latches are already latched by the /LOADSR and
> CLK1B (via UD1), and the Shift Register also by /LOADSR. I'm
> trying to follow you...

The /LOADSR is decoded from the clock counter (16 Mhz). It's jumperable for
011x (J3 - 1 MHz - 40 colums) or x111 (J4 - 2 Mhz - 80 columns). The CLK1B
is the QD output from the counter. UD1 is only needed for 80 columns. For 40
columns this is included in /LOADSR, because the video ram access is
syncronized with the shift register. For 80 columns, the video ram access is
only one from two times, if QD is low.

The latch stores the data when the output from UD1 is high (or /LOADSR and
CLK1B is low). In all the other time the stored data is used. The shift
register is clocked via the 16 MHz (80 columns) or 8 MHz (40 columns). In
one of eigth phases the /LOADSR is low, so the data is loaded into the shift
register and the bit 7 is outputed. So the delay must be 15/16 from the dot

> which line is responsible for delaying the Shift Register? Is it the
> CLK1B (via UE4)?

I don't know what you mean. The delay must be exists, because the access
time from the character rom are some 100 ns. And now i'm knowing why
Christian has problems when he switched from 80 chacaters to 40 characters.
The latches are level triggered viw /LOADSR. But in the middle of the
/LOADSR signal, the dot clock shift the data from the rom into the shift
register. If the access time from the rom must be greater than 1/16 of 1 MHz
or 62.5 ns for 40 columns (or 1/16 of 2 Mhz or 31.25 ns for 80 columns)!
That's a very bad design from commodore!


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Received on 2013-05-02 20:00:04

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