RE: My ColourPET Project

From: Martin Hoffmann-Vetter <>
Date: Thu, 2 May 2013 17:59:43 +0200
Message-ID: <004b01ce474e$10866f30$>
Hello Steve,

> For colour ram make sure that J7 and J8 are NOT connected (J7 is
> normally connected for 40 column - that is the BA0 line).
> I just tried poking $D400 (33792)  and it is active, but not
> appearing onscreen, so we are dealing with a full character offset,
> not just 1 or 2 pixels.

After a short time of thinking, this is by design. The character data and
the color data were readed at the same time. But the character data goes to
the character rom and is stored in the shift register. But this is done one
character cycle later. So you must delayed the color data, too. This is done
with the Disp Ena from the CRTC, too. After the shift register is another
delay. The output is latched with a d flip flop to merge it with the reverse
bit from the video ram. (This reverse bit is delayed with d flip flops.)

So i would say, the color data is 10 pixel to early. You must insert a 8 bit
latch and synchronize it with the load sr signal. After that it must be
delayed by one pixel. Or you use the video signal before the last d flip
flop and extend this flip flop for your rgbi data. So you need only 4 bit.


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Received on 2013-05-02 16:00:42

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