Re: C64 buses when RESET is asserted

From: Jim Brain <>
Date: Mon, 08 Apr 2013 12:36:31 -0500
Message-ID: <>
On 4/8/2013 9:17 AM, Michał Pleban wrote:
> Hello!
> I would like to ask what happens to the address and data bus in the C64
> when the RESET signal is asserted?
> Basically my idea is that for a KERNAL replacement solution, I want to
> have a small SRAM chip instead of the kernal ROM. A PIC microcontroller
> would load the kernal data from SD card to the SRAM upon power-up, then
> shut itself off. If necessary, the MCU would assert a longer RESET
> signal to the CPU to finish this task.
> But I don't know, what happens to the CPU and VIC buses when RESET is
> asserted? Are they driven or tri-stated? Because if they are driven, I
> would need to add some buffers between the PIC and the SRAM, so that
> signals from PIC would not interfere with what the CPU and/or VIC puts
> on the bus during reset, and that would complicate my design...
> Regards,
> Michau.
>         Message was sent through the cbm-hackers mailing list
I still think your idea is fine, just just need to isolate the ADDR and 
DATA bus of the ROM from the PCB socket while you are updating it.  I 
think the PETVet does something similar, though it's doing it on the CPU 
socket, not the ROM socket.


Jim Brain

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Received on 2013-04-08 18:00:04

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