On 10/09/2012 07:55 AM, Kajtár Zsolt wrote: > -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > >>> http://dl.dropbox.com/u/58002657/cbm/c64/rom_adapter_0.png >> >> Looks OK to me... Please check in your circuit if the direct connection >> of pin 13 of the LS00 and pin 3 of the LS11 to +5V is there > > Does not look good to me. A12 is routed through 3 LS gates (from CHAROM) > while CE only on 1. I'm almost sure the address is changing _after_ the CE > was activated. Are you sure there are no hazads there? Yes... A ROM (and an EPROM in read mode) is purely combinational logic. If you change any of the input pins, you get the matching change on the output after tAcc (latest!). You can even tie _CS and _OE of a 27C512 to GND and use it, properly programmed, as a PLA replacement. Now, even with the rather late _CS signals supplied by the PLA, the extra few ns of our logic and the added tAcc of the EPROM, the data should still become valid before the end of the cycle. The question is, why isn't it? And to clear that up, a scope or logic analyzer will be needed. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2012-10-09 16:00:10
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