Re: 6500/1 ROM

From: Gerrit Heitsch <>
Date: Sun, 16 Sep 2012 13:05:08 +0200
Message-ID: <>
On 09/16/2012 12:48 PM, wrote:
> On 2012-09-16, at 05:21, Mike Naberezny wrote:
>>>> CSG's ones have a special "test mode" (see
>>> The requested URL /~rcini/classiccmp/pdf/ds_6500.pdf was not found on this server.
>> Download the datasheet for "6500/1 One-Chip Microcomputer" from this page:
>> The test mode is described briefly on page 8.
> "... Applying +10V signal to the _RES line places 6500/1 in the test mode. While in this mode all memory fetches are made from Port PC.  [...] A program can be loaded into RAM allowing the contents of the instruction ROM to be dumped to any port for external verification."
> Now, how do we understand this?
> "Port PC" is probably Port C (Pins PC0-PC7) /me guesses. Eight bits of data (guessing again) but what about addresses? There is not much of a program to be loaded into the whopping 64 bytes of RAM but should be enough for dumping the ROM. Still /how/ can this be loaded into RAM? And executed?

I wouldn't be surprised it means that no matter what the PC or commands 
say, every memory access (command and data fetch) will redirected to Port C.

So you have to expect what it wants to load and then supply the Byte 
starting from the RESET vector. Sounds like a very painful job to get a 
program into the thing, but it could be done and 64 Bytes RAM are enough 
for a simple copy routine that will just dump the ROM onto another port.


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Received on 2012-09-16 12:00:09

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