# Re: 6702 chip

From: Rhialto <rhialto_at_falu.nl>
Date: Thu, 24 May 2012 21:43:05 +0200
Message-ID: <20120524194305.GA1495@falu.nl>
```On Wed 23 May 2012 at 17:40:03 +0000, William Levak wrote:
>
>
> I was thinking of something simpler.  A fixed length shift register
> that toggles a flip-flop.  Each register would have a "reload"
> value. When the shift register reaches its limit, it toggles the
> flip-flop and reloads.
>
> A different odd number would replace the "reload" with the current
> count, and set the register to "reloed" when it outputs a one.

I'm not really sure what you mean with the above. I can imagine a shift
register, where the bit that shifts out, if it is a 1, toggles a
flipflop. The output (or its inverse) can be the output bit as read from
\$efe0. I'm not sure what you mean with "reaches its limit". If you
mean "has been shifted out all its original bits", how would it know
that?

How is it determined when "a different odd number" is put in? A latch
remembering the previous value, xor-ed with the new odd value?

I have make a little program that (apart from the even numbers) first
writes n1 times an odd number, then 1 time a different odd number, then
n2 times the first odd number again.

This run was with 6 times 3, 1 time 1, 12 times 3. Result of bit 1:
1 1 1 1 1 1
1
1 0 1 1 0 1 1 0 1 1 0 1

Remember that for bit 1 we had found a half-cycle of 3,
and the counter wouldn't advance if the bit was set on odd input values.

There is still a cycle of 3, but if it is a half-cycle then both halves
are now the same so the symmetry is broken. Also, because the input bit
is 1 the counter wasn't supposed to advance but still the output
changes.

The other bits don't seem to deviate from their previous prediction.

The next run was with 6 times 5, 1 time 1, many times 5. Result of bit 2
(nominal half-period of 7):
1 1 1 1 1 1
1
1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1

again a period  of 7, with all ones except for 1 zero in it.
(Certainly doesn't look like the twisted counter register I mentioned)

;change3 ==0401==
100 q = 61408: rem \$efe0
110 e = 0: o1 = 3: o2 = 1
120 n1 = 6: n2 = 12
200 print "start with"; n1; "times"; o1
210 for i = 1 to n1: poke q,e: poke q,o1
220 x = peek(q)
230 gosub 1000: print
240 next
300 print "then 1 time"; o2
310 poke q,e: poke q,o2
320 x = peek(q)
330 gosub 1000: print
400 print "back to"; n2; "times"; o1
410 for i = 1 to n2: poke q,e: poke q,o1
420 x = peek(q)
430 gosub 1000: print
440 next
999 end
1000 b = 128
1010 b\$ = "0": if x and b then b\$ = "1"
1020 print b\$; " ";
1030 b = int(b / 2)
1040 if b > 0 then 1010
1050 print x;
1060 return

>
> On Wed, 23 May 2012, Rhialto wrote:
>
> >On Wed 23 May 2012 at 15:45:17 +0000, William Levak wrote:
> >>I start with one and then increase the number.  If I run 6 cycles
> >
> >which would mean that the counter for bit 0 is back to its starting
> >point
> >
> >>and then enter a three, I get bit one high all the time.  If I run
> >>fewer cycles and enter three I get a cycle with bit one low for
> >>several cycles and then high for one cycle.  I get a similar
> >>sequence for entering 5 as the cecond number, but with bit two
> >>affected.
> >
> >Hmmm let's see if this fits with the mental model I've made.
> >It has been suggested that the individual output bits were made by
> >counter registers (which would be of different lengths, according to
> >their cycle, but fixed for each output bit).
> >
> >The pattern of N zeros and N ones could be generated by a twisted
> >counter register of N bits. (A twisted counter register is basically a
> >shift register where the bit that is shifted out is negated and put back
> >into the other side. So if it starts as all-0, the zeros that shift out
> >come back as 1s at the other side, so after N zeros you get N ones, and
> >the ones then come back as zero again etc).
> >
> >The other possibility is a plain counter register, without the NOT. Then
> >it has to have 2 * N bits, which are initialized as N zeros and N ones.
> >Clearly this is more complicated in hardware, so it seems less likely.
> >
> >So if you write something to the chip that changes the pattern, it would
> >be an obvious theory that it affects 1 bit in the counter regiser. If,
> >after that, you only do the "plain" writes[1], you would no longer get a
> >nice pattern of N zeros and N ones, but after the first N bits, the next
> >N bits you would then get would be the inverse of the first N.
> >
> >If the output is generated by a plain counter register, and you affect
> >one bit in it, you would not get the inverting effect after N bits. This
> >would make it possible to see which of these possibilities is the true
> >one (if either).
> >
> >It may of course be that the bit that is affected isn't the bit that
> >will shift out next, so the effect may be delayed. And it doesn't need
> >to be the same offset for every output bit.
> >
> >[1] whatever that means in practice.
> >
> >-Olaf.
> >--
> >___ Olaf 'Rhialto' Seibert  -- There's no point being grown-up if you
> >\X/ rhialto/at/xs4all.nl    -- can't be childish sometimes. -The 4th Doctor
> >
> >      Message was sent through the cbm-hackers mailing list
> >
>
> wlevak@sdf.lonestar.org
> SDF Public Access UNIX System - http://sdf.lonestar.org
>
>       Message was sent through the cbm-hackers mailing list

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```
Received on 2012-05-24 20:00:33

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