From: Rhialto <*rhialto_at_falu.nl*>

Date: Wed, 23 May 2012 18:29:56 +0200

Message-ID: <20120523162956.GA27338@falu.nl>

Date: Wed, 23 May 2012 18:29:56 +0200

Message-ID: <20120523162956.GA27338@falu.nl>

On Wed 23 May 2012 at 15:45:17 +0000, William Levak wrote: > I start with one and then increase the number. If I run 6 cycles which would mean that the counter for bit 0 is back to its starting point > and then enter a three, I get bit one high all the time. If I run > fewer cycles and enter three I get a cycle with bit one low for > several cycles and then high for one cycle. I get a similar > sequence for entering 5 as the cecond number, but with bit two > affected. Hmmm let's see if this fits with the mental model I've made. It has been suggested that the individual output bits were made by counter registers (which would be of different lengths, according to their cycle, but fixed for each output bit). The pattern of N zeros and N ones could be generated by a twisted counter register of N bits. (A twisted counter register is basically a shift register where the bit that is shifted out is negated and put back into the other side. So if it starts as all-0, the zeros that shift out come back as 1s at the other side, so after N zeros you get N ones, and the ones then come back as zero again etc). The other possibility is a plain counter register, without the NOT. Then it has to have 2 * N bits, which are initialized as N zeros and N ones. Clearly this is more complicated in hardware, so it seems less likely. So if you write something to the chip that changes the pattern, it would be an obvious theory that it affects 1 bit in the counter regiser. If, after that, you only do the "plain" writes[1], you would no longer get a nice pattern of N zeros and N ones, but after the first N bits, the next N bits you would then get would be the inverse of the first N. If the output is generated by a plain counter register, and you affect one bit in it, you would not get the inverting effect after N bits. This would make it possible to see which of these possibilities is the true one (if either). It may of course be that the bit that is affected isn't the bit that will shift out next, so the effect may be delayed. And it doesn't need to be the same offset for every output bit. [1] whatever that means in practice. -Olaf. -- ___ Olaf 'Rhialto' Seibert -- There's no point being grown-up if you \X/ rhialto/at/xs4all.nl -- can't be childish sometimes. -The 4th Doctor Message was sent through the cbm-hackers mailing listReceived on 2012-05-23 17:00:06

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