Hello Michau, > It is built around two 512kx8 SRAM chips and will be very small. I > must check first if interfacing static memory to the expansion bus > would not cause any problems. The address signals at the coprocessor port are multiplexed. So the memory expandion at the expansion port isn't available from the coprocessor board. The other idea is to use two dynamic ram chips 441000 (4 bit with 1Mbit). So you can use the existing multiplexer onboard and must add an additional multiplexer for A8 and A9 at the same manner as the modification from the hsg magazine. You need also the BP0 ... BP3. You can find all the dram data lines D0 ... D7 at a buffer. All the address lines A0 ... A7 are at every onboard dynamic ram.And with the signals at the PLA (incl. the BP0 ... BP3) you can generate the RAS, CAS and WE signals. Only the OE signal isn't simple! ;-) So you must adapter one data buffer, remove the pla and put all needed signals the the expansion board. Remove the onboard rams and route the address lines to the expansion board to. So you need only tree modification! If you cut the data path via the data buffer, you must not remove the onboard ram. But without the onboard rams, you reduce the power! Or you use an old 1MB SIM (30 pin) ... Martin Message was sent through the cbm-hackers mailing listReceived on 2012-05-05 22:00:37
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