Hello, this was already discussed on the forum64.de, but since not everyone is reading that, I'll post it here too. If you take a look at a C64 board with the assy number 250466 (aka 'B3'), you'll notice that it uses 64Kx4 DRAMs and has an unused spot named U11 (plus C27 for the decoupling cap) next to the DRAMs. There is also J3 next to it. I always wondered what this was for and finally got around to check it out and map the signals. Another forum member determined that the pinout matches a 74LS139. J3 determines whether R/_W from the CPU is directly connected to the RAMs or routed through the 74LS139. The other signal supplied to the decoder (enable is tied to GND) is PHI0 and the ouput used will only go LOW if PHI0 is HIGH and R/_W is LOW, effectivly making sure that only the CPU can write to the RAM and a VIC read cycle will always be a read cycle even if R/_W from the CPU takes a bit longer to go HIGH again (which it does). I did put a 74LS139 at U11 (if you want to do it, you need to tie pin 13-15 to GND, otherwise they are floating), added C27 and cut J3, the board still runs as if nothing changed. To me it suggests the board designer suspected that some RAMs might be too fast and interpret a VIC read cycle following a CPU write cycle as another write cycle and wanted to make sure this cannot happen. Most RAMs don't seem to need it as I haven't seen a 250466 with U11 populated and repairing one with faster RAMs (100ns) still doesn't cause problems. This circuit does remind me of the GATE IN signal on the 8501 CPU in the 264 series. The later C64 boards (250469, using the 64pin PLA) no longer connect R/_W from the CPU directly to the DRAMs, they run it through the PLA, making me assume that this circuit (or similiar) was integrated there. Anyone here ever run into 'new RAM too fast' problems with a C64 board? Gerrit Message was sent through the cbm-hackers mailing listReceived on 2012-04-07 18:00:04
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