RE: CPU-Replacement for die 264 series?

From: Bil Herd <bherd_at_mercury-cg.com>
Date: Sat, 24 Mar 2012 22:29:38 -0400
Message-ID: <7141231743c015fc9b1bdbb2b4cc1d55@mail.gmail.com>
Yes the gated R/w line was the major difference, it was to keep the /WE
enable line valid compared to the DRAM cycle instead of the Phi clock
cycle.  I don't remember if any other changes were installed in the
processor later other than I think I remember that the port became a 7
bit.  I seem to remember that if the unused bit isn't always returned as
the same bit then the code could hang, so tie the unused port to 1 or
something if emulating with 8 bit.

I think I did the Gated Read/Write with a 74LS73 only I drove the GR/w
line high, not HiZ.

-----Original Message-----
From: owner-cbm-hackers@musoftware.de
[mailto:owner-cbm-hackers@musoftware.de] On Behalf Of Gerrit Heitsch
Sent: Saturday, March 24, 2012 11:44 AM
To: cbm-hackers@musoftware.de
Subject: CPU-Replacement for die 264 series?

Hello,

we all know that most of the 7501 / 8501 CPUs of the 264 series seem to be
fragile and die easily and are very hard to replace if the one you have
stops working.

Now, the 6510 or 8500 of the C64 doesn't seem to have this problem.
Officially it's not rated for the 1.7MHz the 8501 will run at, but I'd be
surprised if it didn't, at that time all plain 6502 I have seen from MOS
were the 'A'-type, rated for 2 MHz. Since the number of systems sold for
the C64 is much higher, it's much easier to get your hands on a working
6510 or 8500 from an otherwise dead C64. I have one or two spare
6510 I'd be willing to risk as a replacement for dead 6510.

I did a bit of side by side comparision (see below). The only signal I
have a bit of a problem with is how 'Gate In' influences R/_W:

 From the TED system manual:

R/_W is latched by the Gate In line to synchronize between a DRAM memory
cycle and the processor clock cycle. If AEC is low when Gate In makes a
low to high transition, the R/_W line will go to a high impedance state
until the next transition of Gate In and AEC is high prior to the
transition.

It shouldn't be difficult to make that work, but so far I haven't been
able to come up with a small and simple circuit for it. It would be nice
if 2 TTL chips were enough.

The other problem is that the 6510 only has 6 portbits (0-5) while the
8501 has 7. This means it won't be possible to run tape and IEC and even
with only one option used the kernal routines would have to be changed.
I no longer have my ROM listing, so I wouldn't be able to do that part.
Also, they use Bit 6 and Bit 7 for input, which suggests to me either
shifting them into the carry bit or using the BIT command to get their
state. That would mean some extra code (time and spacewise) and could mean
some rather large work.

If you're lucky enough to own a 1551, you'd be able to just ignore the CPU
I/O port...


                _______                 _______
       Phi0 in [1  V   ] _RES     Phi0 [1  V   ] _RES
           RDY [       ] R/_W    _HALT [       ] Phi2
          _IRQ [       ] D0       _IRQ [       ] R/_W
           AEC [   M   ] D1       _NMI [   M   ] D0
           Vcc [   O   ] D2        AEC [   O   ] D1
            A0 [   S   ] D3        Vcc [   S   ] D2
            A1 [       ] D4         A0 [       ] D3
            A2 [   8   ] D5         A1 [   6   ] D4
            A3 [   5   ] D6         A2 [   5   ] D5
            A4 [   0   ] D7         A3 [   1   ] D6
            A5 [   1   ] P0         A4 [   0   ] D7
            A6 [       ] P1         A5 [       ] P0
            A7 [       ] P2         A6 [       ] P1
            A8 [       ] P3         A7 [       ] P2
            A9 [       ] P4         A8 [       ] P3
           A10 [       ] P6         A9 [       ] P4
           A11 [       ] P7        A10 [       ] P5
           A12 [       ] Gate In   A11 [       ] A15
           A13 [       ] A15       A12 [       ] A14
           GND [_______] A14       A13 [_______] GND


              _______
             [1  V   ]
           [ [       ] ]
           [ [       ]-]       8501    6510
           [ [   M   ]-]       ============
           [-[   O   ]-]         1      1     Phi0
           [-[   S   ]-]         2      2     RDY
           [-[       ]-]         3      3     _IRQ
           [-[   6   ]-]         20     21    GND
           [-[   5   ]-]         21     22    A14
           [-[   1   ]-]         22     23    A15
           [-[   0   ]-]         23     (*)
           [-[       ]-]         24     (**)
           [-[       ]-]         25     (**)
           [-[       ]-]         26     (**)
           [-[       ] ]         27     (**)
           [-[       ] ]         40     40    _RES
           [-[       ] ]
           [-[       ] ]
           [-[       ] ]
           [-[_______] ]
           [           ]


    Unused Signals on the 6510: _NMI (needs pullup) and Phi2

    (*)  Gate In Signal, needs extra logic
    (**) Portbits that can't be used 1:1 between 6510 and 8501


Any suggestions, comments or stuff I have overlooked?

  Gerrit


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Received on 2012-03-25 06:00:09

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