On Feb 26, 2012, at 12:02 PM, Gerrit Heitsch wrote: > On 02/26/2012 08:42 PM, Didier Derny wrote: >> I just forgot the sprites.... >> >> I checked the swinSID only the write are supported, R/W is not even >> connected. >> (I tried to emulate an eprom with an avr but I failed, even the "tightest" >> assembler was >> Too slow. Perhaps that it could work with an xmega but the we have the 3v to >> 5v problem.) > > Well, with a 1 MHz 6502, you have less than 500ns from _CS low to deliver the data. That's less than 10 cycles on a 20MHz AVR. > > I think one would need a CPLD or the like to emulate a CIA or VIC and with both you'd have to be cycle-exact since even the one cycle difference between the 6526 and 6526A tripped up some software. Yes, microcontrollers aren't fast enough and you'd be wasting a lot of power busy-waiting on signals. CPLD is the right way to go for low-density designs. You get hundreds to thousands of logic cells and low power usage. Except for Actel, FPGAs require an external microcontroller for loading the SRAM on each power-up. That makes it more expensive and larger footprint. FPGAs are overkill for single-chip replacement. The remaining problems are: * You'd still need an analog stage for both SID and VIC chips, which might take up more of the chip footprint. For example, you'd probably need a few tuned op-amps to do the integration of the SID filter. * The final product would probably cost more than people are willing to spend, given that a working C64 is $10-25 on ebay. So unless chip replacements can be sold for $50 or more, it's probably not worth doing except as a one-off hobby project. -Nate Message was sent through the cbm-hackers mailing listReceived on 2012-02-27 20:00:15
Archive generated by hypermail 2.2.0.