Re: Disabling memory refresh in UltiMax mode Re: 6510 handling of $00 and $01 registers

From: Segher Boessenkool <>
Date: Sat, 10 Dec 2011 20:51:16 +0100
Message-Id: <>
>> Excellent fun! It sees if the light pen interrupt can be triggered
>> between raster lines x'136 and 2; if so, it's a 6569R1, if not, not.
> Did they change the video timing or just the legal lines an LP IRQ  
> can be triggered? On my 1084 monitor, the welcome screen looks OK  
> no matter what VIC I use.

Neither; look at my later message.

>> The discrete vs. CMOS core logic thing seems to check whether  
>> flipping
>> the VIC address space (VA15,VA14) glitches (doesn't on the CMOS).
> In what way does the old PLA design cause a glitch?

I don't know :-)

>> 6526 vs. 8521 CIA checks exactly how long it takes a timer to trigger
>> (8521 is a clock cycle earlier it seems).
> Hm? From what I read everywhere, the HMOS-CIA (8521 or 6526 after  
> week 4x in 1986) takes an extra cycle with the timer IRQ compared  
> to the NMOS 6526.

That is quite possible.  Note the "seems" etc.

> When testing a C64, I use the type check program mentioned above  
> plus a RAM test and the 'Edge of Disgrace' demo. The latter has a  
> few 'plasma' effects and on those you notice that they were written  
> for a 9-luma VIC. On the 6569R1 they look less smooth.

You could just switch the monitor to greyscale :-P

> To bad no one has yet been able to find a software trick to  
> distinguish between the 6510 and the 8500. :)

They didn't?  I thought you could do the timing thing with the high
port pins?  Very unstable of course...


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Received on 2011-12-10 20:00:03

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