Re: Additional SIDs

From: Rainer Buchty <>
Date: Fri, 2 Dec 2011 15:05:51 +0100 (CET)
Message-ID: <alpine.DEB.1.10.1112021428430.7053@athlon>
On Fri, 2 Dec 2011, Richard Atkinson wrote:

> What a strange bug. Presumably BS gets reset along with the phase 
> accumulator value for the sync'ed oscillator. It's an odd bug to creep 
> in though; the phase accumulator value is not processor-visible state 
> whereas the BS bit is part of the Wavetable Size register.

The fun part is that this does not happen for sync but only(!) for AM.

Regarding your question concerning sync/AM, these are controlled by the 
very same bit. All that matters is if it's a even- or odd-numbered 
oscillator. If the sync/AM bit is set for an even voice, the next odd 
voice syncs to the even voice. If set for an odd voice, the odd voice 
AMs the next even voice, i.e.

0 --[sync]--> 1 --[AM]--> 2 --[sync]--> 3 and so on.

For the 3-osc voice structure of the ESQ1/SQ80 this means, that you get 
triplets of odd/even/odd and even/odd/even. Depending on using Sync or 
AM, the voice assigner shuffles around the single osc in order to match 
that above chain with respect to the selected mode.

If you break down the 32 oscs into two chains you therefore get

2x 0s1a2s3a4s5a6s7a8s9aAsBaCsDaEsF

As you see, there's 8 syncs but only 7 AMs in the chain. So you only get 
14 oscillators in total if you want to use AM and sync in an equal 
manner -- either oscs 0-D as 7 sync pairs or 1-E as 7 AM pairs.

> Incidentally, all the documentation I have seen mentions Sync as a 
> mode in the Oscillator Control register, but not AM. I know the chip 
> has AM because it's on the ESQ-1 and SQ-80 front panel. The modes for 
> a single oscillator are Free Run, One Shot, Sync and Swap, using two 
> bits in the Oscillator Control register. But there are two Oscillator 
> Control registers in each pair of oscillators, so there are really 4 
> bits for the combined modes of the two oscillators. What do you get 
> for each of the 16 permutations?

There's no 16 permutations, just 4. There's no control crossing.

The only thing I don't know is whether the toggle mode really works in a 
looped manner, i.e. that even starts odd, then odd starts even.

Personally, I doubt it, from the way the sync chain is implemented. A 
"backward sync path" would not match the overall structure.

Any funky modes as e.g. present in SoundProcess are AFAIK 
software-enforced, triggering an interrupt upon wave end, and leave it 
to the software to react timely. There's one mode which uses a 32k 
transient to gether with a 32k loop -- that would then be toggle on the 
even and loop on the odd oscillator, if done in hardware not via 

> I'm not sure how many of them used phase accumulating oscillators. 
> Some of them, especially instruments like the Fairlight with dedicated 
> memory and CPUs for each voice, may have used divide by N counters. 
> There is a 1 LSB jitter in the access pattern of a phase accumulating 
> oscillator, depending on the frequency value selected, which does not 
> occur with a divide by N counter. This will show up in the final 
> waveform as a deterministic artefact.

PPG was using phase accumulators, although not at 29/39kHz but around 
250kHz update rate.

Need to check the Fairlight schematics whether that one was using 
variable clock rate playback.

> Would be good to put some of the channels through the SID filter, and 
> have the others come out unfiltered. A fixed filter could roll off 
> some unwanted aliasing noise, but without a fixed sample rate it's 
> difficult to know what cutoff frequency to give it.

You do have a fixed sampling rate. The DOC uses phase accumulation, not 
variable clock rates.

Before doing anything else, you enable the desired number of 
oscillators, therefore directly influencing the playback rate:

 	f=f_clk/8*(2+#enabled oscs))

It doesn't matter how many of these you halt or play. Hence, with an 
8MHz clock you can alter the playback rate between ~333kHz (1 enabled 
osc) and ~29kHz (32 enabled oscs).


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Received on 2011-12-02 15:00:08

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