Re: Additional SIDs

From: Rainer Buchty <>
Date: Thu, 1 Dec 2011 22:57:15 +0100 (CET)
Message-ID: <alpine.DEB.2.00.1112012237150.18713@localhost>
On Thu, 1 Dec 2011, Richard Atkinson wrote:

> That looked like the easy option at first glance, but now you've 
> explained the DOC expects to be bus master and generate the other CPU 
> clocks, I think the easiest thing to do would be to have another PLL 
> and generate more or less a copy of the VIC-II dot clock but with 
> timing to suit the DOC. So, the PLL would compare the divided down E 
> or Q clock coming from the DOC with the phi 2 signal coming from the 
> C64, and control an 8MHz VCO for the DOC so as to keep those two in 
> sync.


> Reading the DOC registers should be possible with the PLL solution 
> assuming the DOC read cycle (meant for 6809) is compatible with 6502.

It should. E=1 means CPU bus access, E=0 means DOC bus access.

> As I understand it the basic DOC has a 64K address space and a bank 
> select bit (i.e. A16) for every oscillator.

Right. And that bank select signal has a bug :)

If you set the Sync/AM bit upon sync BS will be cleared, too. That's why 
it was never experienced on the IIGS and ESQ1 (64k machines) and the 
Mirage (128kB but no use of Sync/AM).

> I was actually thinking of sample ROM for a simple C64 implementation, 
> using either the 64K ESQ-1 ROM or perhaps half the 256K SQ-80 ROM. I 
> think the Apple IIGS has 64K of sample RAM, possibly DRAM, and bus 
> arbitration logic to write to either DOC registers or sample RAM. But 
> because the DOC has no method of writing to RAM itself, all logic to 
> select which memory addresses to write to have to be external to the 
> DOC.

I would put it as follows: the DOC only uses $00 to $e2, therefore 
anything up is spare. Within DOC register address space you could then 
hijack $f0-$ff for own registers like address register HSB/MSB/LSB for 

> The implementation questions I'd want to answer: can a digital 
> oscillator chip with 8 bit samples and phase accumulating oscillators 
> sound good - i.e. as good as SID in the aliasing department.

Sure. After all, 29kHz was right in the league of back-then studio 
equipment like the E-mu Emulator II, even Fairlight CMI.

> Is sample ROM enough to make a musically useful instrument (I like my 
> ESQ1!), or does it have to have RAM to be useful, and how much more 
> complex is the logic needed to write to RAM.

In these times, I'd go for RAM. It only takes a 74138 for breaking up 
the DOC window, a 74139 for creating the latch enables for 3 74573 and 
the SRAM's output enable; the second half of 74139 could be used to 
restrict the DOC's CS# to $00-$ef. Or just a GAL22V10.

> How many output channels to support, 1, 2, 4, 8 or 16.

I'd go for 2. That'd then give 16 voices per 2 oscs where the stereo 
panning is done via setting the paired oscs volume.

In case you want to use sync/am, it's probably only 14 or 15 voices due 
to the weird oscillator pairing in hardware.

> Each output channel needs a sample and hold circuit and a low pass 
> filter.

The ESQ1/SQ80 don't use S&H, just a 4051 followed by the CEM3379. So 
presumably a 4051 plus some filter should be fine.


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Received on 2011-12-01 22:00:38

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