Re: Blurry picture

> There are two thing that can drive the data bus relevant to this:  
> it can
> be driven from the data pins, when a signal I call enDin is active;  
> or it
> can be precharged, when preD is active.  So let's look how those are
> generated :-)
>
> We have
>
> 	enDin = (phi1 or (phi2 and enA) or wr) and not 2phi1
> 	preD = 2phi1 and 4phi2
>
> [2phi1 is the first phase of the 2MHz clock, etc.]
> [Why 4phi2 there and not 4phi1?  I have no idea, it could be wrong  
> even]

These are identical between 6569R1 and 8565R2, and the PHI0 output is as
well (it's a very slightly delayed phi2).

> So that is pretty much it: the data pins do not drive the internal VIC
> data bus during the first half of the CPU write to a register (or any
> other VIC 2MHz cycle); the internal data bus is precharged during that
> time.
>
> So then why doesn't it happen on non-C C64...

> I also should look at when
> exactly AEC is generated (I think that is different between 65xx  
> and 85xx
> actually).

The 8565R2 has a slight delay in the AEC circuit, compared to 6569R1;  
but
the silicon is faster, so it's probably just correcting for that.  The
formula for AEC is   not stealing_the_bus and not phi1   .

The AEC signal is also used for generating enA (the enable for address
output from the VIC); the 6569 enables the address pins whenever AEC
is low, while the 8565 waits a 4MHz clock before doing that, whenever
AEC was active before.  The 6569 also uses the AEC signal in the logic
for #CAS, no idea what that's about.

So, as far as I can see, there is no difference big enough to hide the
grey dots on the C64 while they show on the C64C: the grey dots are
usually about half a pixel wide, i.e. 60ns, changing with temperature
and the phase of the moon and such; and they never happen on 6569
machines, so the timing difference is likely at least 100ns.  It's said
even that the colour changes a pixel later on the 6569, which would make
the difference almost 200ns!

An 8500 will react slightly faster to AEC than a 6510, but that's still
not enough.  There are two big board differences as well though: the
C64 has a 1.5kR pullup on R/#W, while the C64C has 3.3kR; and they use
a very different PLA (or custom chip actually, for the C64C).  The  
82S100
PLA used in the C64 has a propagation delay of typical 40ns, max. 80ns.

I calculate 150ns vs. 300ns to pull the R/#W line low with those pullup
values, but someone who knows what he is doing should check that ;-)
(and I do not know the actual drive capability of the 6510: the  
datasheet
says 1 TTL load, but that is a minimum; I took 5mA.  With a combined  
load
of all the chips with R/#W as input of 100pF, I get those delays, but
my calculation is garbage I'm sure).  Another way to check is to just
replace the pullup on a machine and see what that does to the dots, of
course.  Much better than stupid calculations :-P

So which of these is the actual cause, or do I miss the mark again...


Segher


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