Re: 264/TED/Plus4 Story

From: Pasi 'Albert' Ojala <>
Date: Sat, 29 Oct 2011 14:45:54 +0300
Message-ID: <>
On 10/27/11 22:04, Bil Herd wrote:
> like power consumption.  They would lay a small LCD temperature sensing
> thing on the die and then review the hotspots, they found things like a
> transistor acting as a 200ohm resister between power rails, etc.


Even with today's rule checking tools at work our chip layout guys are
stumped with one particular RF design, part of which acts as a current
sink when enabled.

Rule checks are done and redone, the generated masks have been viewed,
visual checks of the layout done over and over, but nothing suspicious 
was found, so the only action left was order a FIB to cut the power 
supply at a strategic location. In a fib they etch open the plastic
mold with acid, then take electron and/or alpha particle beams to cut
the traces of the metal layers of the chip. (Cuts are easy, straps are
harder.) Top metal is easiest, we generally use 5 metal layers.

The cut would at least give some indication where the current
draw is or is not.

Ok, it turned out to be a good guess. The fib was successful, and it
confirmed that the current was going into something that was the only
place that could draw that kind of currents in the chip. We also had
temperature-sensitive liquids in hand so we could've detected hot-spots
using a microscope (the normal photon kind we have in our lab).

Unfortunately, the new information did not tell anything about why that
particular part draws the current it seems to. Now they need to decide
what to try next to get new information.

So, sometimes it is still as hard as back then, and many revisions are
still needed, although the fib process makes chips easier and faster
(than the 3-month lead time) to change for testing of various fixes.

(And yes, the guys at the fab plant could not find a problem with the
  layout either.)


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Received on 2011-10-29 12:00:03

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